Market Overview

Cadence Full-Flow Digital Tool Suite Achieves GLOBALFOUNDRIES 22FDX® Certification



  • Tools certified using the Cadence Tensilica Fusion F1 DSP
  • Cadence digital tool suite optimized for GF 22FDX technology
    enables mutual customers to reach PPA goals faster and deliver new
    products to market with shorter design cycles

Cadence Design Systems, Inc. (NASDAQ:CDNS) today announced that its
full-flow digital tool suite has achieved certification for the
GLOBALFOUNDRIES (GF) 22FDX® process technology. The GF
certification process was completed using the Cadence®
Tensilica® Fusion F1 DSP, which targets internet of things
(IoT) and wearables applications. Through the certification process, the
Cadence tools have been confirmed to meet all of GF's accuracy criteria
for its fully depleted silicon-on-insulator (FD-SOI)
architecture, and customers using the Cadence digital tool suite on the
GF 22FDX process technology can optimize power, performance and area
(PPA) and reduce time-to-market.

For more information on the GF-certified Cadence digital tool suite,
please visit
For more information on the Tensilica Fusion F1 DSP, visit

To facilitate the adoption of GF's 22FDX process technology, the
following Cadence tools that offer 22FDX body bias support are supported
in the GF design flow:

  • Innovus Implementation System:
    An advanced physical implementation tool, incorporating a
    massively parallel architecture that helps designers deliver
    high-quality SoCs in less time with best-in-class PPA
  • Genus Synthesis Solution: An RTL
    synthesis and physical synthesis engine that improves productivity
    challenges faced by RTL designers, delivering up to 5X faster
    synthesis turnaround times
  • Tempus Timing Signoff Solution: A
    complete timing analysis tool that improves signoff timing closure via
    massively parallel processing and physically aware timing optimization
  • Voltus IC Power Integrity Solution: A
    cell-level power integrity solution that supports comprehensive
    electromigration and IR drop (EM/IR) design rules and requirements
    while providing full-chip SoC power signoff accuracy
  • Voltus-Fi Custom Power Integrity Solution: A transistor-level
    power integrity solution that supports comprehensive EM/IR design
    rules and requirements while providing SPICE-level power signoff
    accuracy for analog, memory and custom digital IP blocks
  • QuantusExtraction Solution: A
    single, unified parasitic extraction tool that supports cell-level and
    transistor-level extractions during design implementation and signoff
    and provides best-in-class accuracy versus foundry golden
  • Physical Verification System: Includes advanced technologies
    and rule decks to support design rule checks (DRCs), layout versus
    schematic (LVS), advanced metal fill, voltage-dependent checks and
    in-design verification
  • Litho Physical Analyzer: Signoff solution that enables
    designers to detect and automatically fix process hotspots to improve
    design manufacturability and yield of digital, custom and mixed-signal
    designs, libraries and IP
  • Litho Electrical Analyzer: Allows layout-dependent effect-
    (LDE-) aware re-simulation, layout analysis, matching constraint
    checking, reporting on LDE contributions and the generation of fixing
    guidelines from partial layout to accelerate analog design convergence

GF chose the Fusion F1 DSP to demonstrate the compelling PPA results
with the 22FDX node, which is designed for low-cost, low-energy IoT
sensing and connectivity applications. The Fusion F1 DSP provides the
power-efficient control and signal processing demanded by emerging IoT
applications like NB-IoT-based modems and other battery-powered products.

"Through our collaboration with Cadence, we've verified that the Cadence
methodology meets our accuracy, frequency, power and cell utilization
requirements," said Richard Trihy, senior director, design enablement at
GF. "The certification of the Cadence digital tool suite allows our
mutual customers to reach their PPA targets and to experience the
benefits associated with the GF 22FDX body bias techniques that are key
differentiators with our process technology."

"Through the integration and innovation offered by our full-flow digital
tool suite that was certified using the Tensilica Fusion F1 DSP,
customers designing with the GF 22FDX process technology can converge on
PPA targets faster," said KT Moore, vice president, product management
in the Digital & Signoff Group at Cadence. "GF performed thorough
correlation checks on the Cadence flow, thereby giving users added
confidence that they can successfully implement robust designs quickly
and stay ahead of the competition in their respective markets."

About Cadence

Cadence enables electronic systems and semiconductor companies to create
the innovative end products that are transforming the way people live,
work and play. Cadence software, hardware and semiconductor IP are used
by customers to deliver products to market faster. The company's System
Design Enablement strategy helps customers develop differentiated
products—from chips to boards to systems—in mobile, consumer, cloud
datacenter, automotive, aerospace, IoT, industrial and other market
segments. Cadence is listed as one of Fortune Magazine's 100 Best
Companies to Work For. Learn more at

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Cadence, the Cadence logo and the other Cadence marks found at
are trademarks or registered trademarks of Cadence Design Systems, Inc.
All other trademarks are the property of their respective owners.

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