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Cadence Introduces Voltus-XP Technology With Extensive Parallelism, Up to 5X Acceleration, and Increased Capacity for Power Signoff at Advanced Nodes

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HiSilicon Accelerates Power Signoff in Next-Generation Chip Designs
with Enhanced Cadence Voltus IC Power Integrity Solution

Cadence Design Systems, Inc. (NASDAQ:CDNS) today announced that it has
enhanced the Cadence® Voltus IC Power Integrity
Solution with an extensively parallel (XP) algorithm option employing
distributed processing technology for power grid signoff at
advanced-node process technologies. This new algorithm, which provides
performance improvements up to 5X and works on giga-scale designs,
enhances the Voltus solution's massively parallel execution with more
efficient near-linear performance scalability on thousands of CPUs and
hundreds of machines, and is also cloud ready.

More information on the Voltus IC Power Integrity Solution is available
at www.cadence.com/go/voltushs.

The Voltus-XP technology is ideal for power signoff of very large chip
designs at advanced-process technologies in applications such as mobile,
high-performance computing (HPC), machine learning, artificial
intelligence, networking, automotive, and more. With the new extensive
parallel algorithm also providing much larger capacity than before, any
full-chip SoC designs can now be run flat, not only for power-grid IR
drop and electromigration (EM) analysis but also electrical and thermal
co-analysis at the chip-package-board system level, including 3DIC, with
Cadence Sigrity technologies.

"We have been using the Cadence Voltus IC Power Integrity Solution to
sign off our mobile and HPC production designs because of its high
performance and silicon accuracy," stated Zanfeng Chen, design director
at HiSilicon. "As the semiconductor industry pushes the envelope on
advanced FinFET process nodes, it is crucial that a tool like the Voltus
solution stays ahead of the performance curve and allows us to achieve
24-hour turnaround time for power signoff. We are happy to have verified
that the extensive parallelism in the Voltus solution can deliver the
results in line with our future 5G chip design requirements."

"The Voltus IC Power Integrity Solution is architected for big design
data management with demanding requirements for parallel execution in
chip-power calculation, grid parasitic extraction, IR drop and EM
analysis," said Chin-Chi Teng, Cadence vice president and general
manager, Digital and Signoff Group. "This unique Voltus-XP technology
distributes processing over a large number of machines effectively and
provides a high-performance power signoff solution with silicon-proven
accuracy, which enables our customers to meet their time-to-market
challenges."

About Cadence

Cadence enables electronic systems and semiconductor companies to create
the innovative end products that are transforming the way people live,
work and play. Cadence software, hardware and semiconductor IP are used
by customers to deliver products to market faster. The company's System
Design Enablement strategy helps customers develop differentiated
products—from chips to boards to systems—in mobile, consumer, cloud
datacenter, automotive, aerospace, IoT, industrial and other market
segments. Cadence is listed as one of Fortune Magazine's 100 Best
Companies to Work For. Learn more at www.cadence.com.

© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Cadence, the Cadence logo and the other Cadence marks found at 
www.cadence.com/go/trademarks are
trademarks or registered trademarks of Cadence Design Systems, Inc. All
other trademarks are the property of their respective owners.

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